EDN

Metastability and Clock Uncertainty in FPGA Designs

No discussion on FPGA design is complete without addressing the issues associated with transferring signals that are not synchronized to the clock into clocked logic. While this should be a digital ...
Dezeen

Studio Ayaskan designs clock that rakes sand to illustrate the ripples of time

London design duo Studio Ayaskan has created a clock, which rakes sand in hypnotic, concentric circles to mark the passage of time. The Sand project is a nod to Japanese rock gardens, called ...
EDN

Designs with multiple clock domains: New tools avoid clock skew and reduce pattern counts

Nothing accelerates a testability engineer's receding hairline as the addition of further clock domains to the latest SoC or IC design. Avoiding clock skew during test is becoming one of the biggest ...
autoevolution

MTR Designs’ Ferrofluid Clock Will Bring a Touch of Awesome Into Your Office

If you’re into science and neat gadgets, maybe the Ferrofluid Clock from MTR Designs is the thing for you, as it manages to combine both into an elegant and unique timepiece that’s bound to become the ...
Semiconductor Engineering

Conquer Placement And Clock Tree Challenges In HPC Designs

High-performance computing (HPC) applications require IC designs with maximum performance. However, as process technology advances, achieving high performance has become increasingly challenging.
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...