EDN

Spectral view sharpens jitter testing

A new approach to jitter testing has been devised for leading-edge systems. It takes a spectral view of the jitter that not only allows immediate identification of the sources for debugging but also ...
Design And Reuse

The Architectural Evolution of 16GHz PLLs for Next-Gen AI and SerDes SoCs

To support the data rates of 64Gbps and beyond, we believe a fundamental architectural shift is necessary. This article outlines our R&D team's upcoming PLL suitable for high-speed SerDes having ultra ...
EDN

On-chip VCOs can be digitally tuned

Synchronous systems, whether analog or digital, all use a clock reference signal, typically generated using a high-frequency phase-locked loop (PLL), where power consumption, frequency range and ...
Embedded

Dealing with PLL clock jitter in advanced processor designs: Part 3

Before we discuss the guidelines that the developer must follow when measuring TIE jitter, it is useful to also look at jitter for a much more general case in which jitter is not assumed to be ...
Electronic Design

Jitter Testing – A High-Throughput Jitter Analysis Test Strategy

A promising solution for economical precision test can take your jitters out of jitter testing. Multigigabit high-speed serial (HSS) interfaces like PCI Express, Fibre Chan-nel, XAUI, and Serial ATA ...