This CMOS two-input combination NAND/NOR gate is a three-input, fourpin logic gate. A p-channel enhancementtype MOSFET (Q1) and an n-channel enhancement-type MOSFET (Q4) form one complementary ...
The 74AHC00-Q100; 74AHCT00-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. JESD7-A. The ...
The 74AHC132 and 74AHCT132 are quad 2-input NAND Schmitt triggers classified as high speed silicon gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in ...
Before we plunge headfirst into the fray with gusto and abandon (and aplomb, of course), let’s remind and reassure ourselves that—although the following discussions focus on the devices and ...
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